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motorola semiconductor technical data this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 2003 document order number: mc33882/d rev 3.0, 12/2003 33882 advance information simplified application diagram mcu 33882 v dd v pwr optional parallel control of outputs 0 through 7 optional control of paired outputs sclk si so v dd v pwr in0 in1 in2 in3 in4 in5 gnd out0 out1 out2 out3 out4 out5 in0 & in1 in2 & in3 in4 & in5 mode out6 out7 in6 in7 cs high-powe r outputs low-power led outputs six-output low-side switch with spi and parallel input control the 33882 is a smart six-output low-side switch able to control system loads up to 1.0 a. the six outputs can be controlled via both serial peripheral interface (spi) and parallel input control, making the device attractive for fault- tolerant system applications. there are two additional 30 ma low-side switches with spi diagnostic reporti ng (with parallel in put control only). the 33882 is designed to interface directly with industry-standard microcontrollers via spi to control both inductive and incandescent loads. outputs are configured as open-drain power mosfets incorporating internal dynamic clamping and current limiting. the device has multiple monitoring and protection features, including low st andby current, fault status reporting, internal 52 v clamp on each output, output- specific diagnostics, and protective shutdown. in addition, it has a mode sele ct terminal affording a dual means of input control. features ? outputs clamped for switching inductive loads ? very low operational bias currents (< 2.0 ma) ? cmos input logic compatib le with 5.0 v logic levels ? load dump robust (60 v transient at v pwr on out0?out5) ? daisy chain operation of multiple devices possible ? switch outputs can be paralleled for higher currents ?r ds(on) of 0.4 ? per output (25c) at 13 v v pwr ? spi operation guar anteed to 2.0 mhz six-output lo w-side switch ordering information device temperature range (t a ) package mc33882dh/r2 -40c to 125c 30 hsop mc33882fc/r2 -40c to 125c 32 qfn fc suffix case 1306-01 32-terminal qfn dh suffix case 979a-09 30-terminal hsop 33882 simplified application diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 2 figure 1. 33882 simplified internal block diagram - + - + + - 17 (out7) 30 (out6) 26 (out5) 23 (out4) 20 (out3) 10 (out2) 7 (out1) 5 (out0) 16 (v dd ) 1 (v pwr ) 12 (si) 3 ( mode ) 18 (in7) 29 (in6) 24 (in4) 28 (in4 & in5) 21 (in3) 27 (in5) 9 (in2) 19 (in2 & in3) 6 (in1) 4 (in0) 2 (in0 & in1) 13 (sclk) 14 (cs) 15 (so) serial out serial in dddddd d d cccccc c c qq qq qq q q dd v dd v tri-state shift enable so fault latch/shift register output 0 status output status 1 through 7 gate 0 gate 0 gate 2 gate 3 gate 4 gate 5 gate 6 gate 7 overvoltage shutdown undervoltage shutdown internal bias detect logic on open open load off/on detect load short 3.0 a detect ref v lim i of (th) v o(off) i 40 m a 3.0 v 52 v out6 and out7 unclamped low power out1 to out5 power 01 23 45 67 gnd (heat sink) note terminal numbers shown in this figure are applicable only to the 30-lead hsop package. high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 3 hsop terminal function description terminal terminal name formal name definition 1 v pwr load supply voltage this terminal is connected to battery vo ltage. a decoupling cap is required from v pwr to ground. 2 19 28 in0 & in1 in2 & in3 in4 & in5 input 0 & input 1 input 2 & input 3 input 4 & input 5 these input terminals control two output channels each when the mode terminal is pulled high. these terminals may be connected to pulse width modulated (pwm) outputs of the control ic while the mode terminal is high. the st ates of these terminals are ignored during normal operation ( mode terminal low) and override the normal inputs (serial or parallel) when the mode terminal is high. these terminals have internal active 25 a pull-downs. 3 mode mode select the mode terminal is connected to the mode terminal of the control ic. this terminal has an internal active 25 a pull-up. 4 6 9 18 21 24 27 29 in0 in1 in2 in7 in3 in4 in5 in6 input 0?input7 these are parallel control input terminal s. these terminals have internal 25 a active pull-downs. 5 7 10 17 20 23 26 30 out0 out1 out2 out7 out3 out4 out5 out6 output 0?output7 each terminal is one chann el's drain, sinking current for the respective load. 8, 11, 22, 25 nc no connect not connected. 12 si serial input the serial input terminal is connected to th e spi serial data output terminal of the control ic from where it receives output command data. this input has an internal active 25 a pull-down and requires cmos logic levels. 13 sclk serial clock the sclk terminal of the control ic is a bi t (shift) clock for the spi port. it transitions one time per bit transferred when in operation. it is idle between command transfers. it is 50% duty cycle, and has cmos levels. 14 cs chip select this terminal is connected to a chip select output of the control ic. this input has an internal active 25 a pull-up and requires cmos logic levels. v pwr 1 out0 in1 out1 nc in2 out2 nc si sclk cs so mode in0 in0 & in1 out6 out5 nc in4 out4 nc in3 out3 in2 & in3 in7 out7 v dd in4 & in5 in5 in6 7 8 9 10 11 12 13 14 15 3 4 5 6 2 30 24 23 22 21 20 19 18 17 16 28 27 26 25 29 gnd heat sink f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 4 15 so serial output this terminal is connected to t he spi serial data input terminal of the control ic or to the si terminal of the next dev ice in a daisy chain. this ou tput will remain tri-stated unless the device is selected by a low cs terminal or the mode terminal goes low. the output signal generated will have cmos logic levels and the output data will transition on the falling edges of sclk. the serial output data provides fault information for each output and is returned msb first when the device is addressed. 16 v dd logic supply voltage this terminal is connected to the 5.0 v power supply of the system. a decoupling capacitor is required from v dd to ground. heat sink (exposed pad) gnd ground the exposed pad on this package provides the circuit ground connection for this ic. ground continuity is required for the outputs to turn on. hsop terminal function description (continued) terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 5 qfn terminal function description terminal terminal name formal name definition 7 26 1 in0 & in1 in2 & in3 in4 & in5 input 0 & input 1 input 2 & input 3 input 4 & input 5 these input terminals control two output channels each when the mode terminal is pulled high. these terminals may be connected to pulse width modulated (pwm) outputs of the control ic while the mode terminal is high. the states of these terminals are ignored during normal operation ( mode terminal low) and override the normal inputs (serial or parallel) when the mode terminal is high. these terminals have internal active 25 a pull-downs. 2 9 11 13 25 28 30 32 in6 in0 in1 in2 in7 in3 in4 in5 input 0?input 7 these are parallel input terminals. these terminals have internal 25 a active pull- downs. 3 10 12 14 24 27 29 31 out6 out0 out1 out2 out7 out3 out4 out5 output 0?output 7 each terminal is one chann el's drain, sinking current for the respective load. 4, 5, 19?22 gnd ground ground continuity is required for the outputs to turn on. 6 v pwr load supply voltage this terminal is connected to battery volt age. a decoupling capacitor is required from v pwr to ground. 8 mode mode select the mode terminal is connected to the mode terminal of the control ic. this terminal has an internal active 25 a pull-up. 15 si serial input the serial input terminal is connected to th e spi serial data output terminal of the control ic from where it receives output command data. this input has an internal active 25 a pull-down and requires cmos logic levels. 24 out7 gnd gnd gnd so cs v dd 17 23 22 21 20 19 18 gnd in4 & in5 gnd gnd v pwr in0 & in1 mode in6 out6 in5 out4 in3 out3 in2 & in3 in7 out5 in4 in0 out1 in2 out2 si sclk out0 in1 1 8 2 3 4 5 6 7 9 16 10 11 12 13 14 15 32 25 31 30 29 28 27 26 transparent top view of package f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 6 16 sclk serial clock the sclk terminal of the control ic is a bi t (shift) clock for the spi port. it transitions one time per bit transferred when in operation. it is idle between command transfers. it is 50% duty cycle, and has cmos levels. 17 cs chip select this terminal is connected to a chip select output of the control ic.this input has an internal active 25 a pull-up and requires cmos logic levels. 18 so serial output this terminal is connected to the spi serial da ta input terminal of the control ic or to the si terminal of the next dev ice in a daisy chain. this ou tput will remain tri-stated unless the device is selected by a low cs terminal or the mode terminal goes low. the output signal generated will have cmos logic levels and the output data will transition on the falling edges of sclk. the serial output data provides fault information for each output and is returned msb first when the device is addressed. 23 v dd logic supply voltage this terminal is connected to the 5.0 v power supply of the system. a decoupling capacitor is required from v dd to ground. qfn terminal function description (continued) terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 7 maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value limit electrical ratings load supply voltage normal operation (steady-state) transient survival (note 1) v pwr(ss) v pwr(t) 25 -1.5 to 60 v logic supply voltage (note 2) v dd -0.3 to 7.0 v input terminal voltage (note 3) v in -0.3 to v dd + 0.3 v output clamp voltage (out0 to out5) (note 4) 20 ma = i o = 0.2 a v o(off) 48 to 64 v output self-limit current out0 to out5 out6 and out7 i o(lim) 3.0 to 6.0 0.05 to 0.15 a esd voltage (hsop and qfn) human body model (note 5) machine model (note 6) v esd1 v esd2 2000 200 v output clamp energy (note 7) out0 to out5: single pulse at 1.5 a, t j = 150 c out6 and out7: single pulse at 0.45 a, t j = 150 c e clamp 100 50 mj maximum operating frequency (spi) so (note 8) f of 3.2 mhz thermal ratings storage temperature t stg -55 to 150 c operating junction temperature t j -40 to 150 c terminal soldering temperature hsop qfn t solder 220 240 c notes 1. transient capability with external 100 ? resistor in series with v pwr terminal and supply. 2. exceeding these voltages may cause a malf unction or permanent damage to the device. 3. exceeding the limits on any parallel inputs or spi terminals may cause permanent damage to the device. 4. with output off. 5. esd1 testing is performed in accordance with the human body model (c zap =100 pf, r zap =1500 ? ). 6. esd2 testing is performed in ac cordance with the machine model (c zap =200 pf, r zap =0 ? ). 7. maximum output clamp energy capability at indicate d junction temperature using a single pulse method. 8. serial frequency specifications assume the ic is driving 8 tri-stated devices (20 pf each). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 8 thermal resistance (note 9), (note 10) junction-to-ambient, natural convecti on, single-layer board (1s) (note 11) hsop qfn r ja 41 85 c/w junction-to-ambient, natural convection, four-layer board (2s2p) (note 12) hsop qfn r jma 18 27 c/w junction-to-board (bottom) hsop qfn r jb 3.0 10 c/w junction-to-case (top) (note 13) hsop qfn r jc 0.2 1.2 c/w notes 9. junction temperature is a function of on-chip power dissipation, package thermal re sistance, mounting site (board) temperatur e, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 10. thermal resistance between the die and the printed circuit boar d per jedec jesd51-8. board temperature is measured on the to p surface of the board near the package. 11. per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 12. per jedec jesd51-6 with the board horizontal. 13. indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec 883, method 1012.1) with the cold plate temperature used for the case temperature. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. rating symbol value limit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 9 static electrical characteristics characteristics noted under conditions 4.75 v v dd 5.25 v, 9.0 v v pwr 17 v, -40 c t a 125 c unless otherwise noted. characteristic symbol min typ max unit power input supply voltage ranges functional threshold (note 14) full operation v dd v pwr 5.5 8.0 4.5 ? 8.0 25 v v dd supply current (all outputs on) (note 15) i o = 1.0 a each i pwr(on) ??7.5 ma overvoltage shutdown (note 16) v pwr (ov) 30?40v overvoltage shutdown hysteresis (note 17) v pwr (ov) hys 0.4 ? 1.5 v power-on reset threshold, v dd (note 18) v por 2.5 ? 3.5 v logic supply current (all outputs on) v dd = 5.5 v i dd ??5.0 ma power output output drain-to-source on resistance out0 to out5: t j = 150c, v pwr = 13.0 v, i o = 1.0 a r ds(on) ?0.60.8 ? output drain-to-source on resistance out0 to out5: t j = 25c, v pwr = 13.0 v, i o = 1.0 a r ds(on) ? 0.4 0.6 ? output self-limiting current v pwr = 13.0 v, v dd = 4.5 v, v in = 5.0 v i o(lim) 3.0 ? 6.0 a open load off detection (outputs programmed off) v off(th) 2.5 ? 3.5 v output off (open load detect) drain current (output terminals programmed off) (note 19) out0 to out5 out6 and out7 i o(off) 20 20 ? ? 120 80 a output on (open load detect) dr ain current (output terminals programmed on) (note 20) ? 20 ? 200 ma output clamp voltage out0 to out5: i o = 20 ma, t clamp = 100 s v ok 48 52 64 v output leakage current v dd = v pwr = 0.5 v, v out = 24 v i olk ?1.010 a drain-to-source diode forward voltage i sd = 1.0 ma @ 25c i sd = 1.0 ma @ 125c v sd ? ? ? ? 1.4 0.9 v notes 14. outputs of device functionally turn-on (r ds(on) = 0.95 ? @125 c ). spi/parallel inputs and power outputs are operational. fault detection and reporting may not be fully operational within this range. 15. value reflects all outputs on and equally conducting 1.0 a each. v pwr = 5.5 v, cs = 5.0 v. 16. an overvoltage condition will cause any enabled outputs to latch off (disabled). 17. this parameter is guaranteed by design; however, it is not production tested. 18. for v dd less than the power-on reset voltage, all outputs are dis abled and the serial fault register is reset to all 0s. 19. drain current per output with v pwr = 24 v and v load = 9.0 v. 20. drain current per output with v pwr = 13 v, v load = 9.0 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 10 digital interface si logic high siv ih 4.0 ? ? v si logic low siv il ??2.0v cs and sclk logic high cs v ih 3.0 ? ? v cs and sclk logic low cs v il ??3.0v input logic high v ih 3.15 ? ? v input logic low v il ? ? 1.35 v input pull-down current (note 21) v in = 1.5 v i in(pd) 5.0 ? 25 a input pull-up current (note 22) v in = 3.5 v i in(pu) -25 ? -5.0 a so and high-state output voltage i oh = -1.0 ma v soh 3.5 ? ? v so and low-state output voltage i ol = 1.0 ma v sol 0?0.4 v so and tri-state leakage current cs = 0.7 v dd , v so = 0.3 v dd cs = 0.7 v dd , v so = 0.7 v dd i sot -10 ? ? ? ? 10 a input capacitance (note 23) 0 = v in = 5.5 v c in ??12 pf so and tri-state capacitance (note 24) 0 = v in = 5.5 v c sot ??20 pf notes 21. inputs si, in0 & in1, in2 & in3, in4 & in5, and in0 to in7 inco rporate active internal pull-down current sinks for noise imm unity enhancement. 22. the mode and cs inputs incorporate active internal pull-up current sources for noi se immunity enhancement. 23. this parameter applies to inputs si, cs , sclk, mode , in0 & in1, in2 & in3, in4 & in5, and in0 to in7. it is guaranteed by design; however, it is not production tested. 24. this parameter applies to the off state (tri-stated) condition of so and is guaranteed by design; however, it is not product ion tested. static electrical charac teristics (continued) characteristics noted under conditions 4.75 v v dd 5.25 v, 9.0 v v pwr 17 v, -40 c t a 125 c unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 11 dynamic electrical characteristics characteristics noted under conditions 4.75 v v dd 5.25 v, 9.0 v v pwr 17 v, -40 c t a 125 c unless otherwise noted. characteristic symbol min typ max unit power output timing output rise time (note 25) t r 1.0 ? 10 s output fall time (note 25) t f 1.0 ? 10 s output turn-on delay time (note 26) t dly (on) 1.0 ? 10 s output turn-off delay time (note 27) t dly(off) 1.0 ? 10 s output short fault sense time (note 28) r load = < 1.0 v t ss 25 ? 100 s output short fault refresh time (note 29) r load = < 1.0 v t ref 3.0 4.5 6.0 ms output off open load sense time (note 30) t os(off) 25 60 100 s output on open load sense time (note 31) t os(on) 3.0 ? 12 ms output short fault on duty cycle (note 32) sc dc 0.42 ? 3.22 % digital interface timing sclk clock high time (sclk = 3.2 mhz) (note 33) t sclkh ? ? 141 ns sclk clock low time (sclk = 3.2 mhz) (note 33) t sclkl ? ? 141 ns falling edge (0.8 v) of cs to rising edge (2.0 v) of sclk required setup time (note 33) t lead ? ? 140 ns falling edge (0.8 v) of sclk to rising edge (2.0 v) of cs required setup time (note 33) t lag ??50 ns si, cs , sclk incoming signal rise time (note 33) t rsi ? ? 50 ns si, cs , sclk incoming signal fall time (note 33) t fsi ? ? 50 ns notes 25. output rise and fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15 ? resistive load to a v bat of 15 v, v pwr =15v. 26. output turn-on delay time m easured from rising edge (3.0 v) v in ( cs for serial) to 90% v o using a 15 ? load to a v bat of 15 v, v pwr =15v. 27. output turn-off delay time measured from falling edge (1.0 v) v in (3.0 v rising edge of cs for serial) to 10% v o using a 15 ? load to a v bat of 15 v, v pwr = 15 v. 28. the shorted output is turned on during t ss to retry and check if the short has cleared. th e shorted output is in current limit during t ss . the t ss is measured from the start of current limit to the end of current limit. 29. the short fault refresh time is the waiting period between t ss retry signals. the shorted output is disabled during this refresh time. the t ref is measured from the end of current limit to the start of current limit. 30. the t os(off) is measured from the time the faulted out put is turned off until the fault bit is avai lable to be loaded into the internal fau lt register. to guarantee a fault is reported on so, the falling edge of cs must occur at least 100 s after the faulted output is off. 31. the t os(on) is measured from the time the faulted output is turned on unt il the fault bit is available to be loaded into the internal faul t register. to guarantee a fault is reported on so, the falling edge of cs must occur at least 12 ms after the faulted output is on. 32. percent output short fault on duty cycle is defined as (t ss ) (t ref ) x 100. this specification item is provided fyi and is not tested. 33. parameter is not tested and values suggested are for system design consideration only in prev enting the occurrence of double pulsing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 12 si setup to rising edge (2.0 v) of sclk (at 3.2 mhz) required setup time (note 34) t sisu ??45 ns so setup to sclk rising (2.0 v)/falling (0.8 v) edge required setup time (note 34) t sosu 90 ? ? ns si hold after rising edge (2.0 v) of sclk (at 3.2 mhz) required hold time (note 34) t sihold ??45 ns so hold after sclk rising (2.0 v)/falling (0.8 v) edge required hold time (note 34) t sohold 90 ? ? ns so rise time c l = 200 pf t rso ??50 ns so fall time c l = 200 pf t fso ? ?50 ns falling edge of cs (0.8 v) to so low-impedance (note 35) t soen ??110ns rising edge of cs (2.0 v) to so high-impedance (note 36) t sodis ??110ns falling edge of sclk (0.8 v) to so data valid c l = 200 pf at 3.2 mhz (note 37) t sovalid ?6580 ns cs rising edge to next falling edge (note 34) xfer delay ? ? 1.0 s notes 34. parameter is not tested and values suggested are for system design consideration only in prev enting the occurrence of double pulsing. 35. enable time required for so. pull-up resistor = 10 k ? . 36. disable time required for so. pull-up resistor = 10 k ? . 37. time required to obtain valid data out of so following the falling edge of sclk. dynamic electrical characteristics (continued) characteristics noted under conditions 4.75 v v dd 5.25 v, 9.0 v v pwr 17 v, -40 c t a 125 c unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 13 timing diagrams figure 2. short occurring while on, ending during refresh (i load = 1.0 a) figure 3. short occurring while on, ending during retry (i load = 1.0 a) gate x = command signal at the gate of driver x fault bit x = internal fault register bit state tref x = first refresh time may be less than tref iload = 1a normal operation p ut x a te x u t x ult bit x fault fault iload 0a tref tref tref tref idlim tssa on off shorted load / short - to - vbat 5v 0v short occurs while on, ends during refresh p ut x a te x u t x u lt bit x idlim iload 0a on off 5v 0v s b tssd tssd input x gate x i out x 5.0 v 0 v on off i load 0 a i o(lim) fault bit x shorted load/short-to-v pwr t ref t ref t ssd t ssa t ssd t ref t ref fault fault input x gate x i out x 5.0 v 0 v on i load 0 a i o(lim) fault bit x off off cb gate x = command signal at the gate of driver x fault bit x = internal fault register bit state t ref x = first refresh time may be less than t ref i load = 1.0 a normal operation shorted operation gate x = command signal at the gate of driver x fault bit x = internal fault register bit state tref x = first refresh time may be less than tref iload = 1a normal operation put x a te x ut x a ult bit x fault fault iload 0a tref tref tref tref idlim tssa on off shorted load / short - to - vbat 5v 0v short occurs while on, ends during retry p ut x a te x ut x a ult bit x idlim iload 0a on off 5v 0v s b tssd tssd gate x = command signal at the gate of driver x fault bit x = internal fault register bit state t ref x = first refresh time may be less than t ref i load = 1.0 a input x gate x i out x 5.0 v 0 v on i load 0 a i o(lim) fault bit x input x gate x i out x 5.0 v 0 v on i load 0 a i o(lim) fault bit x off cb shorted load/short-to-v pwr t ssd t ref t ref t ssd t ssa t ref t ref fault fault shorted operation normal operation off f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 14 figure 4. short occurring while on, ending during refresh (i load = 20 ma) figure 5. short occurring while on, ending during retry (i load = 20 ma) gate x = command signal at the gate of driver x fault bit x = internal fault register bit state tref x = first refresh time may be less than tref iload = 20ma put x a te x ut x a ult bit x fault fault iload 0a tref tref tref tref idlim tssd on off shorted load / short - to - vbat 5v 0v short occurs while on, ends during refresh p ut x a te x ut x a ult bit x idlim iload 0a on off 5v 0v s b tssa input x gate x i out x 5.0 v 0 v on i load 0 a i o(lim) fault bit x off input x gate x i out x 5.0 v 0 v on i load 0 a i o(lim) fault bit x off cb shorted load/short-to-v pwr gate x = command signal at the gate of driver x fault bit x = internal fault register bit state t ref x = first refresh time may be less than t ref i load = 20 ma fault fault t ref t ref t ref t ref t ssa t ssd normal operation shorted operation gate x = command signal at the gate of driver x fault bit x = internal fault register bit state tref x = first refresh time may be less than tref iload = 20ma normal operation n put x ate x o ut x a ult bit x fault fault iload 0a tref tref tref tref idlim tssd on off shorted load / short - to - vbat 5v 0v short occurs while on, ends during retry put x a te x o ut x a ult bit x idlim iload 0a on off 5v 0v s b tssd tssa gate x = command signal at the gate of driver x fault bit x = internal fault register bit state t ref x = first refresh time may be less than t ref i load = 20 ma input x gate x i out x 5.0 v 0 v on i load 0 a i o(lim) fault bit x off cb input x gate x i out x 5.0 v 0 v on i load 0 a i o(lim) fault bit x off fault fault t ref t ref t ref t ref t ssa t ssd t ssd shorted load/short-to-v pwr shorted operation normal operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 15 electrical performance curves figure 6. output r ds(on) versus temperature figure 7. output clamp voltage versus temperature 0.37 0.38 ambient temperature (c) ohms 55 70 115 40 85 100 130 0.39 0.4 0.41 0.42 0.36 0.35 0.43 r ds(on) 25 ambient temperature ( c) volts -50 0 25 100 -25 50 75 125 53.8 54.0 54.2 54.4 54.6 54.8 53.6 53.4 55.0 v clamp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 16 table 1. logic table mode of operation command sent status transmitted so status transmitted next so default terminal hpw01 hpw45 input terminals 5 4 3 2 1 0 gates 5 4 3 2 1 0 outputs 5 4 3 2 1 0 normal operation 00111111 001x1010 000101x1 00xxx000 00000000 00000000 00000000 00000000 00111111 001y1010 000101y1 00yyy000 l l l l x x x x x x x x x x x x x x x h x l x l l x l x h x h h h l l l h h h h h h h h h l h l l h l h h h h h h l l l l l l l l l l l l h l h h l h l l l l l l h h h default mode 00xxxxxx 00xxxxxx 00xxxxxx 00xxxxxx 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 h h h h h h l l h l h l x x h l x x x x l h x x x x h l x x x x l h x x h h h l h h h h l h l l l l h l h h l l l h l l l l l h l l l l h l h h h h l h l l h h h l h h overvoltage shutdown 00xxxxxx 00xxxxxx 00xxxxxx x x x x x x x x x l l l l l l h h h h h h short-to-battery / short circuit output 0 00xxxxx0 00xxxxx1 00000000 00000001 00yyyyy0 00yyyyy0 l l x x x x x x x x x l x x x x x x y y y y y l y y y y y h y y y y y h y y y y y h open load/ short-to-ground output 0 00xxxxx0 00xxxxx1 00000001 00000000 00yyyyy1 00yyyyy1 l l x x x x x x x x x l x x x x x x y y y y y l y y y y y h y y y y y l y y y y y l legend 0011xxyy = serial (spi) commands and status bytes (8-bit operation mode) msb to lsb. 0 = off command, so ok status. 1 = on command, so fault status. x = don?t care. y = defined by state of x. h = high-voltage level: active state for inputs/gates, inactive state for outputs. l = low-voltage level: inactive state for inputs/gates, active state for outputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 17 system/application information introduction the 33882 incorporates six 1.0 a low-side switches using both serial peripheral interface (spi) i/o as well as optional parallel input control to each output. there are also two low- power (30 ma) low-side switches with spi diagnostic feedback, but parallel-only input control. the 33882 incorporates smartmos technology with cmos logic, bipolar/mos analog circuitry, and dmos power mosfets. designed to interface directly with a microcontr oller, it controls inductive or incandescent loads. each output is configured as an open drain transistor with dynamic clamping. functional terminal description v pwr terminal the v pwr terminal is connected to battery voltage. this supply is provided for overvoltage shutdown protection and for added gate drive capabilities. a decoupling capacitor is required from v pwr to ground. in0 & in1, in2 & in3, and in4 & in5 terminals these input terminals control two output channels each when the mode terminal is pulled high: in0 & in1 controls out0 and out1, in2 & in3 cont rols out2 and out3, while in4 & in5 controls out4 and out5. these terminals may be connected to pwm outputs of the control ic and pulled high or pulled low to control output channel states while the mode terminal is high. the states of these terminals are ignored during normal operation ( mode terminal low) and override the normal inputs (serial or parallel) when the mode terminal is high. these terminals have internal active 25 a pull-downs. mode terminal the mode terminal is connected to the mode terminal of the control ic. this terminal has an internal active 25 a pull-up. when pulled high, the mode terminal does the following: ? disables all serial control of the outputs while still reading any serial input commands. ? disables parallel inputs in0, in1, in2, in3, in4, and in5 control of the outputs. ? selects in0 & in1, in2 & in3, and in4 & in5 input terminals for control of out0 and out1, out2 and out3, out4 and out5, respectively. ? turns off out6 and out7. ? tri-states the so terminal. in0 to in7 terminals these are parallel input term inals connected to output terminals of the control ic. each parallel input is logic high with the corresponding spi control bit to control each output channel. these terminals have internal 25 a active pull- downs. out0 to out7 terminals each terminal is one channel's low-side switch output. out0 to out5 are actively clamped to handle inductive loads. si terminal the serial input terminal is connected to the spi serial data output terminal of the control ic from where it receives output command data. this input has an internal active 25 a pull- down and requires cmos logic levels. the serial data transmitted on this line is an 8- or 16-bit control command sent msb first, controlling the six out put channels. bits a5 through a0 control channels 5 through 0, respectively. bits a6 and a7 enable on open load fault detection on channels 5 through 0. the control ic will ensure that data is available on the rising edge of sclk. each channel has its serial control bit high with its parallel input to determine its state. sclk terminal the sclk terminal of the control ic is a bit (shift) clock for the spi port. it transitions one time per bit transferred when in operation. it is idle between co mmand transfers. it is 50% duty cycle and has cmos levels. this si gnal is used to shift data to and from the device. for proper fault reporting operation, the sclk input must be low when cs transitions from high to low. cs terminal the cs terminal is connected to a chip select output of the control ic. the control ic controls which device is addressed by pulling the cs terminal of the desired device low, enabling the spi communication with the device, while other devices on the serial link keep their serial out puts tri-stated. this input has an internal active 25 a pull-up and requires cmos logic levels. so terminal the serial output terminal is connected to the spi serial data input terminal of the control ic or to the si terminal of the next device in a daisy chain. th is output will remain tri-stated unless the device is selected by a low cs terminal or the mode terminal goes low. the output signal generated will have cmos logic levels and the output data will transition on the falling edges of sclk. the serial output data provides fault information for each output and is returned msb first when the device is addressed. fault bit assignments for return data are as follows: msb-0 through msb-7 are output fault bits for out7 to out0, respectively. in 8-bit spi mode, under normal conditions, the so terminal (not daisy chained) returns all 0s, representing no faults. if a fault is present, a 1 is returned for the appropriate bit. in 16-bit sp i mode, sending a double command byte will provide a command verification byte following the fault f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 18 status byte returned from the so terminal (non-daisy chained). with the mode terminal high, the serial output terminal tri- states. if nothing is connected to the so terminal except an external 10 k ? pull-up resistor, data is read as all 1s by the control ic. v dd terminal this terminal is connected to the 5.0 v power supply of the system. a decoupling capacitor is required from v dd to ground. performance features normal operation out0 to out7 are independent during normal operation. out0 to out5 may be driven serially or by their parallel input terminals. out6 and out7 can only be controlled by their parallel input terminals. device operation is considered normal only if the following conditions apply: ?v pwr of 5.5 v to 24 v and v dd voltage of 4.75 v to 5.25 v. ? junction temperatures less than 150 c. ? for each output, drain voltage exceeds the open load off detection voltage, specif ied in the specification table, while the output is off. for open load detection, an open condition existing for less than the open load detection time, specified in the specification table, is not considered a fault nor is it reported to the fault status register. ?the mode terminal is held at the logic low level, keeping the serial channel/parallel input terminals in control of the eight outputs. serial/parallel input control input control is accomplished by the serial control byte sent via the spi port from the control ic or by the parallel control terminals for each channel. for channels 0 to 5 with serial and parallel control the output state is determined by the or of the serial bit and the parallel input terminal state. serial communication is initiat ed by a low state on the cs terminal and timed by the sclk signal. after cs switches low, the ic initiates eight or 16 clock pulses with the control bits being available on the si terminal at the rising edge of sclk. the bits are transferred in descending bit - significant order. any fault or mode indications on bits returned are logic [1]s. the last six bits are the command signals to the six outputs. upon completion of the serial communication the cs terminal will switch high. this terminates the communication with the slave device and loads the control bits just received to the output channels. upon device power - up, the serial register is cleared. in the application for non - daisy chain configurations, the number of spi devices available to be driven by the so terminal is limited to eight devices. serial status output serial output information sent on the spi port is a check on the fault status of each output channel as well as a check for mode initiation. serial command verification is also possible. so terminal operation the so terminal provides spi status, allowing daisy chaining. the status bits returned to the ic are the fault register bits with logic [1]s indicating a fault on the designated output or mode if all bits return logic [1] (with a 10 k ? pull-up resistor on the so terminal). a command verifi cation is possible if the spi mode is switched to 16 bits. the first byte (8 bits) returned would be the fault status, while the second byte returned would be the first byte sent feeding through the 33882 ic. the second command byte sent would be latched into the 33882 ic. the cs terminal switching low i ndicates the device is selected for serial commun ication with the ic. once cs switches low, the fault status r egister cannot receive new fault information and serial communication begins. as the control bits are clocked from the ic msb first, they are received on rising sclk edges at the si terminal. the fault status bits transition on the so terminal on falling sclk edges and are sampled on rising sclk edges at the input terminal of the ic spi device. when the command bit transmissions for serial communication are complete, the cs terminal is switched high. this terminates communication with the device. the so terminal tri-states, the fault status register is opened to accept new fault information, and the transmitted command data is loaded to the outputs. at the same time, the ic can read the status byte it received. daisy chain operation (o nly possible with so terminal) daisy chain configurations can be used with the so terminal to save cs outputs on the ic. clocking and terminal operations are as defined in the so terminal operation paragraph. for daisy chaining two 8-bit devices, a 16-bit spi command is sent, the first command byte for the second daisy chain device and the second command byte for t he first daisy chain device. a command verification is possible if the spi mode is switched to 32 bits. the first word sent is command verification data fed through the two 33882 ics. data returned in the 32 bits is the two fault status bytes, followed by the first word sent. bits sent out are sampled on rising sclk edges at the input terminal of the next ic in the daisy chain. note because so terminals of the 33882 ics are tri-stated, any device receiving its spi data from a previous 33882 ic so terminal in a daisy chain will not receive data if the mode terminal is low. this prohibits setting spi-controlled channels on with a spi command while the mode terminal is low. therefore, all channels remain off when the mode terminal changes from low to high at vehicle power-up. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 19 mode operation during normal operation output channels are controlled by either the serial input control bits or the parallel input terminals. if the mode terminal is pulled high: ? serial input control is disabled. ? parallel input terminals in0 to in5 are ignored. ? the so terminal is tri-stated. out0 and out1, out2 and out3, and out4 and out5 are controlled by the in0 & in1, in2 & in3, and in4 & in5 terminals, respectively. when a 10 k ? pull-up resistor is used, a logic high on the mode terminal or an open serial output terminal is flagged by the spi when all bits are returned as logic [1]s. although a logic high on the mode terminal disables serial control of outputs, data can still be clocked into the serial input register. this allows programm ing of a desired state for the outputs taking effect only when the mode terminal returns to a logic low. for applications using the so terminal, daisy chaining is permitted, but if the mode terminal is high, writing to other than the first ic in a daisy chain is not possible because the serial outputs are tri-stated. output drivers the high-power out0 to out5 outputs are active clamped, low-side switches driving 1.0 a typical or less loads. the low- power out6 and out7 outputs are unclamped low-side switches driving 30 ma typical or less loads. all outputs are individually protected from shor t circuit or short-to-battery conditions and transient vo ltages. the outputs are also protected by short circuit de vice shutdown. each output individually detects and reports open load/short-to-ground and short circuit/short-to-battery faults. fault sense/protection circuitry each output channel individually detects shorted loads/ short-to-battery while the output is on and open load/short-to- ground while the output is off. out0 to out5 may also be programmed via spi bits 6 and 7 to detect open loads and shorts-to-ground while the output is on. whenever a short or open fault condition is present on a particular output channel, its fault bit in the internal fault register indicates the fault with a logic [1]. when a fault ends, its fault bit remains set until the spi register is read, then it returns to a logic [0], indicating a normal condition. when the cs terminal is pulled low for serial communication, the fault bits in th e internal fault register latch, preventing erroneous status tr ansmissions and the forthcoming communication reports this latched fault status. the so terminal serial output data for 8-bit spi mode are the fault status register bits. for 16-bit spi mode and so terminal (non-daisy chained) use, a transmitted double comm and provides the fault byte followed by the first byte of the double command, becoming a command verification. the status is sent back to the ic for fault monitoring. diagnostic interpretation of the following fault types can be accomplished using the procedure described in the paragraph entitled extensive fault diagnostics , page 20: ? communication error ? open load/short-to-ground ? short-to-battery or short circuit when serial communication is ended, the cs terminal returns high, opening the fault status register to new fault information and tri-stating the so terminal. two fault conditions initiate protective action by the device: ? a short circuit or short-to-battery on a particular output will cause that output to go into a low duty cycle operation until the fault condition is removed or the input to that channel turns off. ? a short circuit condition causes all channels to shut down, ignoring serial and parallel inputs to the device. to be detected and reported as a fault, a fault condition must last a specified time (fault sense time or fault mask time). this prevents any normal switching transients from causing inadvertent fault status indications. fault status information should be ignored for v bat levels outside the 9.0 v to 17 v range. the fault reporting may appear to function properly but may not be 100 percent reliable. short circuit/short-to-battery sensing and protection when an output is turned on, if the drain current limit is reached, the current remains at the limit until the short circuit sense time, t ss , has elapsed. at this time, the affected output will shut down and its fault status bit switches to a logic [1]. the output goes into a low duty cycle operation as long as the short circuit condition exists and the input to that channel is on. this duty cycle is defined by t he sense and refresh times. if a short occurs after the output is on, the faul t sense time indicates the fault and enters the low duty cycle mode at much less than t ss . the duty cycle is low eno ugh to keep the driver from exceeding its thermal capabilities. when the short is removed, the driver resumes no rmal operation at the next retry, but the fault status bit does not return to a normal logic [0] state until it is read from the spi. when the cs terminal of this device is pulled low, the fault status bits are latched, after which any new fault information is not a part of this serial communication event. the low duty cycle operation for a short circuit condition is required to protect the output. it is possible to override this duty cycle if the input signal (parallel or spi) turns the channel on and off faster than 10 khz. for this reason control signals should not exceed this frequency. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 20 open load/short-to-ground while off sensing if the drain voltage falls below the open load off detection voltage at turn off for a period of time exceeding the open load sense time, the fault status bit for this output switches to a logic [1]. if a drain voltage falls below the open load off detection voltage threshold when the output has been off, a fault is indicated with a delay much less than the open load sense time. when the fault is removed, normal operation resumes and the fault status bit will return to a normal logic [0] state. when the cs terminal of this device is pulled low, the fault status bits are latched, after which any new fault information is not part of this serial communication event. overvoltage sensing and protection when v pwr exceeds the overvoltage shutdown threshold, all channels are shut down. serial input data and parallel inputs are ignored. the device resume s normal operation when the v pwr voltage drops below the overvoltage shutdown hysteresis voltage. during over voltage shutdown, some faults may appear to report accurately; however, fault sensing operation is only guaranteed for battery voltage levels from 9.0 v to 17 v. fault status monitoring requirements for serially controlled outputs, so terminal fault monitoring over the serial channel by the ic requires a minimal amount of overhead for normal operation. each status byte received consists of all logic [0]s when faults are not present. if any logic [1]s are returned, a communication error occurred, an output fault occurred, or the mode terminal has been set low. upon receiving any logic [1] bits, the ic must resend the last command, verifying the returned logic [1]s, or correct any communication error. a 16-bit spi transmission with a double command byte to this 8-bit device allows verification of the command (second byte returned) in addition to the fault byte (first byte returned). the command (second) byte returned should mirror the bits sent unless a communication erro r occurred, in which case the command resent should accomplish the correction. if the returned logic [1] validates, it may indicate a mode terminal high or a confirmed out put fault. if it was a confirmed output fault, extensive diagnostics could be performed, determining the fault type, especially if vehicle service is being performed. if all bits return high and verify such, the ic must verify sending a logic low to the mode terminal. it should then resend the command, verifying the mode terminal is at a logic low level, allowing resumption of a normal operation. if all logic [1]s are again returned, there is an open so line, an open mode line, or the spi is not functioning. if the fault does not verify on the command resend, normal operation is resumed. the error could be a communication mistake, a momentary output fault, or a fault condition no longer sensed due to switching the state of the output. for the first two cases, normal operation is resumed and the software continues its normal functions. however, in the third case, additional commands are required for extensive diagnosis of the fault type if this information is mandatory. extensive fault diagnostics more extensive diagnosis may be required under the following conditions: ? when the fault type of a c onfirmed fault is desired, the following scenarios are possible: ? if msb-2 to msb-7 indicates a fault, it is an open load/ short-to-ground fault if the output is off when the fault is reported because only open load/short-to- ground sensing remains operable while an output is off. ? if the output is on when the fault is reported, the fault is a short circuit/short-to-battery if on open load detection is not enabled via spi. if on open load detection is enabled, it must be disabled and the fault status reread. if the fault rema ins, it is a short circuit/ short-to-battery or it is an open load/short-to-ground. ? if msb-0 to msb-2 indicates a fault, it is an open load/ short-to-ground fault if the output is off when the fault is reported becaus e only open load/short-to- ground sensing remains operable while an output is off. ? if the output is on when the fault is reported, the fault is a short circuit/short-to-battery. ? when a fault did not confirm on resend, the fault could either be an short circuit/short-to-battery fault, not sensed when turned off; an open load/s hort-to-ground fault, not sensed when turned on; or a corrected communication error. to determine if it is an output fault condition, the faulted output must be turned back to its previous state with a new command. this command should be sent twice to read the status after the output is latched in this state, thus confirming the faul t and reporting it again. parallel control of outputs is a mode of control, potentially requiring extensive diagnostics if a fault is reported. this is because parallel control signals are completely asynchronous to the serial commands. status reports for parallel controlled outputs could require additional information exchange in software to: ? avoid status reads when outpu ts are transitioned, thereby avoiding fault masking times. ? obtain the state of a faulted output for determining fault type (if required). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 21 system actuator electrical characteristics (at room temperature) all drains should have a 0.01 f filter capacitor connected to ground. any unused output terminal should not be energized. a 20 ? resistor to the battery is required to prevent false open load reporting. there must also be a maximum of 100 ? of resistance from v pwr to ground, keeping battery-powered loads off when the ic is powered down. however, all loads should be powered by v pwr to protect the device from full transient voltages on the battery voltage. power-up the device is insensitive to power sequencing for v pwr and v dd , as well as intolerant to latch-up on all i/o terminals. upon power-up, an internal power-on reset clears the serial registers, allowing all outputs to power up in the off-state when parallel control terminals are also low. although the serial register is cleared by this powe r-on reset, software must still initialize the outputs with an spi command prior to changing the mode terminal from a high to a low state. this assures known output states when mode is low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33882 motorola analog integrated circuit device data 22 package dimensions seating plane gauge plane datum plane bottom view detail y 3.404 11.1 14.45 16 0.8 28x b m 0.20 c 30 16 15 1 2.7 1.1 12.6 7.3 a m 0.20 c 1.1 w w 0.20 c 0.35 0.152 detail y section w ? w 0.475 0.28 0.432 0.32 2.9 heatsink area b a c h .127 c n 30x 4x 1 max 4x 1 max pin one id 1.1 max x 45? ?5? 15.8 2.5 2x 10.9 13.95 0.9 2x 3 3.3 2.9 2.7 11.7 6.121 exposed 0.23 0.23 0.35 0.35 0.84 0.025 8? max notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m, 1994. 3. datum plane ? h ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. dimensions d and e1 do not include mold protrusion. allowable protrusion is 0.150 per side. dimensions d and e1 do include mold mismatch and are determined at datum plane ? h ? . 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. 6. datums ? a ? and ? b ? t o be determined at datum plane ? h ? . 7. dimension d does not include tiebar protrusions. allowable tiebar protrusions are 0.150 per side. (1.6) dh suffix 30-terminal hsop plastic package case 979a-09 issue h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33882 23 n pin 1 index area exposed die attach pad 4.55 25 8 1 32 4.85 32x 0.23 7 b c 0.1 2x 2x c 0.1 a 7 24 17 16 9 0.65 0.325 m 0.1 c m 0.05 c a b 32x 0.75 c 0.1 a b c 0.1 a b m m view m-m notes: 1. all dimensions are in millimeters. 2. dimensioning and to lerancing per asme y14.5m, 1994. 3. the complete jedec designator for this package is: hf-pqfp-n. 4. corner chamfer may not be present. dimensions of optional features are for reference only. 5. coplanarity applies to leads, corner leads and die attach pad. 6. for anvil singulated qfn packages, maximum draft angle is 12 o . detail m pin 1 index (2.53) 4 preferred corner configuration detail n (0.25) 4 detail n corner configuration option 0.60 0.60 detail m preferred backside pin 1 index detail t detail t preferred backside pin 1 index (90) 2x detail m backside pin 1 index option 1.0 1.00 0.05 c 0.1 c 0.05 c seating plane 5 detail g view rotated 90 clockwise o (0.65) (0.325) 0.8 0.75 0.00 0.065 32x (45 ) 0.015 2x 0.39 0.31 0.24 0.24 0.1 0.0 4.55 4.85 28x 0.37 0.50 2.4 0.475 0.425 2.3 backside pin 1 index 0.25 0.15 r fc suffix 32-terminal qfn plastic package case 1306-01 issue d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: motorola literature distribution: p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information cent er, 3-20-1 minami-azabu. minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre , 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. 852-26668334 technical information center: 1-800-521-6274 mc33882/d motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limit ation consequential or incidental damages. ?typical? parameters can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not c onvey any license under its patent rights nor the rights of oth ers. motorola products are not designed, intended, or authorized for use as components in system s intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other appl ication in which the failur e of the motorola product could create a situation where persona l injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and h old motorola and its officers, employees, subsidiaries, affiliate s, and distributors harmless against all cl aims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal in jury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc . motorola, inc. is an equal opportunity/affirmative action employer. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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